This invention relates generally to insulated gate field-effect transistors (IGFETS), and more particularly the invention relates to reducing gate to drain capacitance in IGFETS including lateral and vertical MOSFETS, especially for use with high frequency power MOSFET devices.
Reduction of gate to drain feedback capacitance (C.sub.gd or C.sub.rss) in MOSFET devices is desired in order to maximize RF gain and minimize signal distortion. C.sub.gd is critical since it is effectively multiplied by the voltage gain of the device or C.sub.effective =C.sub.rss (1+gmR.sub.1) where gm is the transconductance and R.sub.1 is the load impedance.
Adler et al., U.S. Pat. No. 5,252,848 discloses an FET structure which includes a performance enhancing conductor shield covering the gate electrode and a portion of the drain region of the FET. A description of such a device operating as a 2 GHz RF transistor is in Technical Digest IEDM conference, 1996, pages 87-90. While the external shield reportedly reduces C.sub.gd, the dominant component of C.sub.gd (gate over drain next to channel) is not shielded. Further, while the external shield is applicable to lateral MOS transistors (LDMOS), the external shield cannot be used with vertical transistors. Additionally, process costs in fabricating such devices can be high.
Copending patent application Ser. No. 08/905,513 filed Aug. 4, 1997, now U.S. Pat. No. 14987-42, discloses a field effect transistor including a lateral MOSFET (LDMOS) and a vertical MOSFET (DMOS) transistor which has reduced gate to drain capacitance by providing a buried shield plate underlying the gate and between the gate and drain of the transistor. More particularly, the transistor comprises a semiconductor body having a major surface, a source region of first conductivity type abutting the surface, a drain region of the first conductivity type abutting the surface and spaced from the source region by a channel of a second conductivity type opposite to the first conductivity type, and a gate electrode overlying the channel and part of the drain and insulated therefrom by a dielectric material. The shield plate is formed prior to the gate and is positioned under the gate and between the gate and the drain and is insulated therefrom. The shield plate preferably includes a contact for electrically biasing the shield plate such as by a fixed DC potential and/or an AC ground potential through a capacitive element. While the structure is an improvement over this structure in U.S. Pat. No. 5,252,848, supra, the gate overlapping the shield plate does not reduce input capacitance.
The present invention is directed to a MOSFET structure having effective reduction of gate to drain parasitic capacitance and reduction of input capacitance.